An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM
Joung-Wook Moon, H. J. Yoo, Hundai Choi, Il-Won Park, Seok-Yong Kang, Jun-Bae Kim, Haeyoung Chung, Kiho Kim, Dong-Hun Lee, Ki‐Jae Song, Seok-Hun Hyun, Indal Song, Young‐Soo Sohn, Yong-Ho Cho, Jung-Hwan Choi, Kwang‐Il Park, Seong-Jin Jang · 2018
This paper presents a wide-frequency-range, self-calibrating, built-off-test (BOT) transceiver for a DDR4 SDRAM interface. The proposed BOT transceiver consists of a data transceiver, a phase-locked loop, a delay-locked loop, a self-timing calibration (STC) circuit with a 90-degree phase shifter, and a self-voltage calibration (SVC) circuit. In particular, with both the STC and SVC circuits, data channel skew is effectively compensated, and the voltage margin can be maximized while the DDR4 SDRAM is communicating with the test equipment. The BOT transceiver is realized in 20-nm DRAM CMOS technology. Using the fabricated BOT transceiver, we have successfully demonstrated 3.2-Gb/s/pin testing for DDR4 SDRAM with a 1.0-V supply voltage.