Opportunistic compression for direct-mapped DRAM caches
Alaa R. Alameldeen, Rajat Agarwal · Proceedings of the International Symposium on Memory Systems · 2018
Large off-chip DRAM caches offer performance and bandwidth improvements for many systems by bridging the gap between on-chip last level caches and off-chip memories. To avoid the high hit latency resulting from serial DRAM accesses for tags and data, prior work proposed co-locating tags and data to be accessed together. The state-of-the-art block-based DRAM cache design, the Alloy Cache, reduces hit latency but suffers from increased miss rate due to its direct-mapped design.