Low Power and Area Efficient 256-bit Shift Register based on Pulsed Latches
Janardhan, K. V., Mouli, K. Chandra · Zenodo (CERN European Organization for Nuclear Research) · 2018
Shift Registers are the basic building blocks in VLSI design. Power and Area in the Shift Registers can be reduced by replacing the Flip Flops with Pulsed Latches. Delay has less importance in this method as we are not introducing any circuit elements either in between the flip flops or in between the latches. While shifting the data there arises a timing problem between the pulsed latches. To eliminate the timing problem between the latches multiple non-overlapped delayed pulsed clock signals are introduced instead of a single pulsed clock. By grouping the latches to several sub-shifter registers and adding the temporary storage latch per each sub-shifter register involves in the design to make n-bit Shift Register. The proposed Shift Register at VDD =1.8volts and 100MHZ clock frequency saves 37% area and 44% of power compared to conventional Shift Register with Flip Flops.