Design of a Bit Error Ratio Testing and Error Correction System Based on High-Speed Serial Interface
Lingjun Zhu, Jian Wang, Jinmei Lai · 2018
This paper presents the design and implementation of a Bit Error Ratio Testing (BERT) and error correction system based on high-speed serial interfaces. On-chip and off-chip loopback methods are used to implement dual-channel high-speed serial data transmission. 7 optional test pattern generators based on pseudorandom binary sequence (PRBS) are applied to single or automated BERT. An efficient error correction method based on even parity matrix is proposed, and implemented with a receiver data FIFO and a shift register. A control program is designed for dynamic test configuration, test result output and user interface. Experimental results show that the data transmission rate of the system reaches 3 Gbit/s; the measurable range of BER in a single test is 2-34to 1; the error correction methods can remarkably reduce error bits when the BER is lower than 2-20, with an overhead of 12.5%.