Verifying an Implementation of Genetic Algorithm on FPGA-SoC using SystemVerilog
Hayder Al-Hakeem, Suvi Karhu, Jarmo T. Alander · Linköping electronic conference proceedings · 2018
In this paper we show how an efficient implementation of genetic algorithms can be done on Field Programmable Gate Array i.e. on programmable hardware using the latest hardware design language aiding verification.A fourway number partitioning problem of 128 unsigned 16-bit integers is used as a test case of the implementation.However, other similar problems could be solved using the proposed approach.The design was implemented using a combination of reusable verified intellectual property cores for arithmetic operations and VHDL to describe the genetic algorithm operators in register transfer level.The register transfer level components were verified in ModelSim using SystemVerilog assertions and covergroups.Test results show significant improvements in performance compared to C language implementation running on a core i-7 desktop computer.