Error Bit Distributions in Triple-level Cell Three-dimensional (3D) NAND Flash Memory
Rui Cao, Jixuan Wu, Wenjing Yang, Yuan Li, Jiezhi Chen · 2018
In this work, aiming at a deep understanding on the reliability properties of three-dimensional (3D) NAND flash memory, error bit distributions of 3D TLC (triple-level cell) NAND flash memory are characterized by using the customized NAND testing platform. On the one side, it is found that the error bit degradation during program/erase (P/E) cycling is dominated by the least significant bit (LSB) page, where 1 to 0 is the major contribution; on the other side, with a further study on error bit distributions as a function of the program page number, four distinct distribution regions are identified in the case of LSB page.