Designs and implementations of ultra-low power, low voltage digital signal processors
Le Ba Ngoc · 2018
Conventional Fast Fourier Transform (FFT) using Radix-2 2 brought a significant improvement in FFT implementations to reduce circuit complexity and computational power.One of the most well-known architectures for VLSI implementation in Radix-2 2 is Single-path Delay Feedback (SDF) which has simple architecture and requires the smallest amount of memory.However, low throughput due to the single data line is its major drawback.In the first part of this thesis, Radix-2 2 Multiple-path Delay Commutator (MDC) architecture is proposed to achieve higher throughput while preserving low memory and hardware usage to reduce energy per conversion.In addition, a new input scheduling algorithm, parallelpipelined architecture together with ultra-low power circuit design techniques are employed to increase the speed and minimize the total power consumption.A 1024point high speed, ultra-low power Fast Fourier Transform (FFT) was fabricated using STM 65nm technology.The chip consumes 77.2 nJ/FFT with clock frequency of 400 MHz at 0.6V supply and it is able to operate at up to 600MHz at VDD=1V yielding