RTL Level Instruction Profiling for CPU Throttling to Reduce Wasted Dynamic Power
Abdullah A. Owahid, Eugene B John · 2017
This paper identifies a set of instructions suitable for fine grained CPU throttling to reduce wasted dynamic power in RISCV architecture. An EDA flow was developed to process pipeline trace at an early stage. Instruction profile was generated for each benchmark programs that contains all the instructions executed with their occurrence count and stall count at the pipeline stages. A weight based system was introduced to rank them in the instruction profile. It was observed that higher stall causing instructions are repeating across all the benchmark programs. The weight distribution of each benchmark also shows that there are top 20 instructions that have exponentially higher weights than others. The weight system was further extended across all the benchmark programs in the same test suite to select the top 10 instructions for throttling that identifies probable throttling clock cycles and respective pipeline stages. These results can enable researchers to identify bottleneck in architecture at an early stage.