FPGA Based Logic Analyzer
Cristian Zet, Cristian Foşalău · 2018
The present paper presents the design of a logic analyzer and its implementation in FPGA. It is able to simultaneously acquire up to 8 signals, in 32 to 128 samples bursts. Programmable sampling rates are available. Acquired data is transferred to a host computer via a serial interface to be visualized. The paper details the building blocks of the logic analyzer from hardware to waveforms. A LabView application which drives the data exchange between the computer and the analyzer and displays the data is also presented within the paper. Experimental results and conclusions prove the usefulness of the design.