Design of Carry Skip Adder using Concatenation and Incrementation Scheme
Puja Ramesh Khunte · Helix · 2018
In Today's digital world biggest challenge is to reduce delay for increasing speed and efficiency of digital devices.In carry skip adder to achieve high speed we need to lower the path delay.Where, the carry generated should be driven to the output as fast as possible, thereby in results reduces the worst path delay which determines the ultimate corresponding speed of the digital structure.In Conventional Carry Skip Adder (Conv-CSKA), the speed enhancement parameter can be achieved by using concatenation and incrementation schemes.In this paper to achieve high speed, multiplexer logic in Conventional CSKA structure is replaced by AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) compound gates.