Logic synthesis of low power FSM for LUT-based FPGA
Marcin Kubica, Krzysztof Kajstura, Dariusz Kania · AIP conference proceedings · 2018
The paper presents selected elements of logic synthesis of low power FSM. Authors focus on the problem of low power coding for internal states. Proposed coding algorithm leads to reduction of the number of switches and as a result reduction of dynamic power consumption. The paper shows, that effective coding algorithm is insufficient for effective FSM synthesis. A vital role in logic synthesis plays technology mapping. This process requires appropriate function decomposition. The paper presents methods of carrying out technology mapping which uses triangle tables. This method leads to appropriate decomposition path. The experimental results show that effective states coding must be associated with effective technology mapping.