DFT Methodologies for Reducing Shift Power of Compression Architecture for 28NM ASIC
Priyanka N. Solanki, Nilesh Ranpura, Yogesh D. Parmar · 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI) · 2018
As integrated circuit feature size is continuously shrinking, test data reduction and power consumption have become a great challenge. In DFT, scan testing considers as an important aspect to avoid destructive chips and improve yield. Test data reduction can be accomplished by scan compression architecture which also helps to reduce test cost of integrated circuits. This paper presents different shift power reduction techniques for scan compression architecture with their advantages and disadvantages. Here we have focused on the latest technique called shift power group architecture introduced by Synopsys. It helps to reduce average and peak shift power of the design.