Efficient design methods for FIR digital filters
Miriam Guadalupe Cruz Jiménez · LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) · 2017
The design of low-complexity linear-phase Finite Impulse Response (FIR) filters is investigated in this thesis. The proposals developed here are particularly useful for digital communication applications. An efficient and essential method to achieve low complexity is to split the filters into simple subfilters, and among the most important subfilters for such purpose are the comb and cosine filters. These filters have a low computational complexity and a low utilization of hardware resources but very poor magnitude characteristics. In this sense, novel architectures have been developed in the present thesis using the comb and cosine filters as a basis. The resulting architectures, especially useful for low-pass narrowband filtering in sampling rate conversion, achieve better magnitude characteristics and better trade-offs in power, area and speed compared with previous systems recently developed in literature that rely in simple subfilters as well. For filters with constant coefficients, an effective method to realize low-complexity filters is to express the coefficients without multipliers, which are the most expensive elements in terms of area, power and speed. For this case, the proposed contribution focuses on the implementation of the constant multiplications as a network of additions and shifts. Novel theoretical lower bounds for the number of pipelined operations that are needed in Single Constant Multiplication (SCM) and Multiple Constant Multiplication (MCM) blocks have beendeveloped here. These lower bounds have been stablished under the consideration that every operation (addition or subtraction) can have n inputs, and the cost of a pipelined operation is the same as the cost of a single pipeline register. The aforementioned consideration is particularly important because it occurs in the newest families of Field Programmable Gate Arrays (FPGAs), which currently are a preferred platform for the implementation of DSP algorithms.