Cognitive Processing Hardware Elements; Reconfigurable Architecture for Improved Soar Execution (RAISE)
Matthew Scarpino, Robert E. Wray · PsycEXTRA Dataset · 2005
With help from Soar Technology, rule processing has been compared with both FPGAs and x8086 processors. For regular combinatorial logic, FPGAs present a speed-up of over x14000. However, they are presently unable to perform associative memory operations (pointer logic) that many rules require to operate. This shortcoming may be resolved with a dedicated memory management unit. The proof-of-concept RAISE system has been successfully designed and demonstrated. It uses a Virtex-II FPGA to implement a minor Soar application. A GUI allows users to send Working Memory Elements (WMEs) through a serial connection and receive results from the operators. The source code for the FPGA and GUI are in Appendices A and E. The first part of the Hoplite Guide to Run-time Reconfigurable Computing has been made available for free. Many have downloaded it and all comments have been positive.