Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal
Mario Garrido · IEEE Transactions on Circuits & Systems II Express Briefs · 2018
This brief presents novel circuits for calculating the bit reversal on parallel data. The circuits consist of delays/memories and multiplexers, and have the advantage that they requires the minimum number of multiplexers among circuits for parallel bit reversal so far, as well as a small total memory.