Implementation of FPGA‐based MPLS‐TP linear protection switching for 4000 + tunnels in packet transport network for optical carrier Ethernet
YongWook Ra, Junseong Bang, Jeong‐dong Ryoo · IET Communications · 2018
A packet transport network (PTN) for optical carrier Ethernet needs to be reliable even in a case that a fault occurs on a data path. To survive from the network fault, protection switching which sends data traffic to a pre‐established backup path can be implemented on optical PTN systems. Linear protection switching in a multi‐protocol label switching – transport profile (MPLS‐TP) environment requires to be performed with sub‐50 ms for multiple faults on data paths (i.e. tunnels). The linear protection switching for the recovery from multiple faults at almost ten tunnels can be processed on CPU. In this study, a packet transport layer protection switching integrated circuit (PPSI) is developed to increase the number of multiple protection switchings (e.g. 4000 + tunnels) with satisfying the strict requirement on sub‐50 ms switching time, by processing on a field‐programmable gate array (FPGA). The performance of this FPGA implementation is compared with that of the processed on CPU. Furthermore, this study investigates four message forwarding methods of set‐bridge‐and‐selector and automatic protection coordination protocol messages to enhance the performance of the PPSI. The four methods are evaluated using an FPGA test‐bed, in terms of switching time and the number of tunnels.