Improved Simulated Annealing Genetic Algorithm based Low power mapping for 3D NoC
Hanna He, Fang Fang, Wei Wang · MATEC Web of Conferences · 2018
Mapping of IP(Intellectual Property) cores onto NoC(Network-on-Chip) architectures is a key step in NoCbased designs. Energy is the key parameter to measure the designs. Therefore, we propose an Improved Simulated Annealing Genetic Alogrithm, abbreviated as ISAGA. The algorithm combines the parallelism of Genetic Algorithm(GA) and the local search ability of Simulated Annealing(SA). We improve the initial population selection of GA to get the lower power consumption mapping scheme. The experimental results show that compared with the GA, ISAGA has good convergence and can search the optimal solution quickly, which can effectively reduce the power consumption of the system. In the case of 124 IP cores, the average power consumption of the ISAGA is reduced by 32.0% compared with the GA.