Power Efficient Speaker Verification Using Linear Predictive Coding on FPGA
Amit Sravan Bora, R. Dinesh Reddy, Srinath Satpathy, H. Balachander, V. Vijendra, Gaurav Trivedi, Rohit Sinha · 2018
Speaker verification is of great importance, especially in the field of forensics and security. This paper aims at implementing such a system at the hardware level. This system extracts features from the fresh voice samples and verifies the speaker by comparing those with the ones being stored in the database. The features used here are the Linear Predictive Coding (LPC) Coefficients which are obtained using the Levinson - Durbin (LD) algorithm. This paper proposes to implement Vector Quantization (VQ) to obtain the representative LPC vectors. A simple speaker verification system for a single person is efficiently implemented on FPGA.