A Methodology to Validate the On-Chip Buses of a Microcontroller
Meghashyam Ashwathnarayan, Jayakrishna Guddeti · 2018
Post-Silicon Validation is the last level of inspecting the silicon before it is delivered to the customer. With increasing functional complexity and levels of integration of real time, safety-critical applications, design complexity, aggressive scaling, and decrease in time to market, it is imperative to test the robustness of the On-Chip Buses. Safety standards such as IEC 61508 and ISO26262 mandate more robust products and functional safety concepts in automotive and industrial applications. This brief proposes a method to validate the On-Chip Buses of the AURIX Microcontroller. AURIX Instruction Set Generator tool is to generate randomized instructions to execute a block of functionality/task. This allows generating different randomized instructions to execute and also exercise different combinations of Instructions. The goal and objective of the paper is to generate multiple set of instructions which execute the same functionality/task. There by allowing the validation engineer to validate numerous combination of instructions which perform a specific functionality. Finally, our experiments demonstrate that the proposed methodology is capable of generating and agitating various multiple set of instructions, and also stresses the silicon, increasing the likelihood of uncovering a bug at the post-silicon stage.