Security in Design for Testability (DFT)
Rahul Pandey, Sakshee Pandey, C.S Mohammed Shaul Hammed · 2017
Post production testing is necessary to ensure that chip is not having any manufacturing defect, for which Design for Testability techniques are used from past many decade. Scan based design for testability are highly used to increase the controllability and observability of the internal nodes of the circuit. Scan chain help us to test the circuit but on the other hand it give access to the internal node of the chip to unauthorized user which can be considered as security risk as it can lead to information leakage which retrieves secret key used for encryption and decryption in cryptographic cores. This paper proposes a new secure architecture which prevents unauthorized user to test the chip thus providing security to DFT structure. A two level secure architecture is proposed to provide security to cryptographic core against scan based attack.