Power Optimized TPG for BIST Architecture
Manjunath Mosalgi, Ganapathi Hegde · 2017
Now a days low power consumption is essential for portable computing devices and mobile operated devices. BIST is a technique to make chip self testable and to achieve this facility we are adding extra circuitry inside the chip. These extra circuitry will consumes more power. In this paper a new method has been proposed for reducing a shift power for BIST architecture. This is done by modifying LFSR to skip the unnecessary shift operations while generating test patterns by using clock gating technique. Above architecture is implemented for stuck at faults and experimental results shows 15% reduction in power with area overhead is 11%.