Firmware Generation Architecture for Memory BIST
David Sargsyan · 2018
The safety and reliability requirements for automotive SoCs are becoming stronger requiring more complex and flexible solutions. Hardware implementation of test algorithms in memory built-in self-test (BIST) scheme allows in-field testing only with predefined instructions which restricts flexibility of system test in mission mode. In this paper, firmware generation architecture for memory BIST is described which allows to control mission mode access to embedded memories and makes the in-field testing more flexible.