2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS
Mark A Anders, Himanshu Kaul, Sanu K. Mathew, Vikram Suresh, Sudhir K. Satpathy, Amit Agarwal, Steven Hsu, Ram Kumar Krishnamurthy · 2018
A 4×4 node systolic matrix-multiply accelerator with unified INT8/INTI6/FPI6 datapath and wide INT24/INT48/FP32 accumulators is fabricated in 14nm CMOS. Handshake-based routing circuits with multiple-node broadcast enable 8.8× higher energy-efficiency with 20% nonzero sparse matrices. INT8 mode reconfigures each node from lxl to 2×2 matrix multiplier for 2.9TOPS/W energy efficiency at 750mV, and up to 11.3TOPS/W at 280mV (near-threshold).