A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference
Bruce Fleischer, Sunil Kumar Shukla, Matthew M. Ziegler, Joel A. Silberman, Jinwook Oh, Vijavalakshmi Srinivasan, Jungwook Choi, Silvia Melitta Mueller, Ankur Kumar Agrawal, Tina Babinsky, Nianzheng Cao, Chia‐Yu Chen, Pierce Chuang, Thomas Fox, George D. Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo · 2018
A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers. With a programmable architecture and custom ISA, this engine achieves >90% sustained utilization across the range of neural network topologies by employing a dataflow architecture and an on-chip scratchpad hierarchy. Compute precision is optimized at 16b floating point (fp 16) for high model accuracy in training and inference as well as 1b/2b (bi-nary/ternary) integer for aggressive inference performance. At 1.5 GHz, the AI core prototype achieves 1.5 TFLOPS fp 16, 12 TOPS ternary, or 24 TOPS binary peak performance in 14nm CMOS.