UCOMIPSIM 2.0: Pipelined MIPS Architecture Simulator
Andrés Gersnoviez, María Brox, Miguel A. Montijano, Juan A. Sujar, C. Moreno · 2018
The objective of this work is the realization of an application in JAVA whose function will be to simulate the MIPS 32-bit architecture in pipelined computer with hardwired control unit, in order to help in the learning and understanding of this architecture by the students in Computer Architecture subjects. With it, students will be able to graphically visualize the datapath of multiple MIPS instructions passing through the different stages of the pipelined computer.