Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesign
Tony Nowatzki, Newsha Ardalani, Karthikeyan Sankaralingam, Jian Weng · 2018
Recent programmable accelerators are faster and more energy efficient than general purpose processors, but expose complex hardware/software abstractions for compilers. A key problem is instruction scheduling, which requires sophisticated algorithms for mapping instructions to distributed processing elements, routing of operand dependences, and timing the arrival of operands to enable high throughput.