High throughput fault‐resilient AES architecture
Saeideh Sheikhpour, Ali Khayatzadeh Mahani, Nasour Bagheri · IET Computers & Digital Techniques · 2018
As more and more confidential information is being transmitted securely, the use of cryptographic algorithms is expanded. However, existing cryptographic algorithms are subject to various malicious attacks. Fault injection attack is one of the most effective attacks that are able to extract private information with the inexpensive requirement and short amount of time. AES is a block cipher that is used in many critical applications. Here, a lightweight error‐detection architecture for AES has been proposed; the authors call it as high throughput fault‐resilient AES (HFA). In the proposed architecture, the authors use parallel AES architecture, which contains four equivalent blocks and split each block into two pipeline stages. The authors have shown that HFA achieves high error‐detection rate while keeping overheads reasonable.