Radix-4 DIT FFT implementation using Fused Floating-Point Arithmetic Unit
Rajeev Gowda B R, A. B. Kalpana · International journal of advance research, ideas and innovations in technology · 2018
The paper presents a hardware implementation of radix-4 DIT FFT butterfly-unit using Fused Floating-point Arithmetic Unit (FFAU) technique. The proposed FFAU is more efficient in area and delay than the primitive floating-point arithmetic operation. The radix-4 DIT FFT using FFAU is designed and synthesized in cadence using 45nm technology. The non pipelined conventional architecture of FFT operates in 6Mhz whereas proposed FFT architecture operates on 10 Mhz frequency. The outcome area is 46% efficient than the conventional FFT architecture. The 16 point DIT FFT is also implemented on the same proposed FFAU, to ensure the computation speed.