FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing
Khyamling A. Parane, Prasad Prabhu B.M., and Basavaraj Talawar · 2018
In this paper, we present fast and parameterized FPGA based Network-on-Chip (NoC) simulation acceleration framework with automated HDL generation engine. The framework supports the NoC architecture design parameters such as topology, routing algorithms, link width, buffer size, flow control and traffic patterns. The parameterized, high performance and lightweight nature of proposed NoC based framework makes the ideal choice for NoC research studies. The Mesh based topologies have been considered for the experimentation purpose. A congestion aware adaptive routing has been proposed along with the conventional XY routing. Also, parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on the NoC behavior. The adaptive routing algorithm for Mesh based topologies has negligible FPGA area overhead compared to the conventional XY routing. Employing the adaptive routing algorithm, the average packet latency is reduced by 55% under transpose traffic pattern when compared to the XY routing algorithm. The speedup of 2548x has been observed compared to Booksim software simulator. The proposed framework is 2.54x and 25x times faster compared to CONNECT and DART FPGA based simulators respectively.