Reduced Message-Passing Bitwidth for Hardware Implementation of ADMM-LP Decoding
Omar Samhan, Stark C. Draper · 2018
We consider the implementation in hardware of linear-programming (LP) decoding for low-density parity-check (LDPC) codes. Previous work has shown that the alternating direction method of multipliers (ADMM) can be applied to solve LP decoding in a message passing manner amenable to hardware. Wasson et al. demonstrated the feasibility of a hardware implementation in a field-programmable gate array (FPGA). However, the area footprint and message bit-width of the implemenation was not competitive with classic alternatives such as min-sum decoding. In this paper we leverage recent work by Jiao et al. on implementating the central computational primative of ADMM-LP decoding (a certain Euclidean projection) via look-up tables (LUTs). While Jiao's work indicated the possiblity of significant bit-width reduction, it left open a number of questions about how to translate those ideas into hardware and what algorithmic modifications would be required. In this paper we answer those questions and develop a modified version of Wasson's ADMM-LP decoding algorithm, realizing a bit-width reduction of about 50%, thereby yielding a hardware implementation of ADMM-LP decoding that is competitive with min-sum.