Joint Crosstalk Avoidance with Multiple Bit Error Correction Coding Technique for NoC Interconnect
T Siva Teja, T. Kiran, T. V. Narayana, M. Vinodhini, N. S. Murty · 2018
In an On-chip communication where the devices have scaled down to nanometer scale, a single chip contains numerous processing elements and inter-communication between these elements is Network on chip. Glitches in NoC or the disturbances in the physical environment of NoC leads to multiple-bit errors. These leads to the loss of data communicated and may cause need for retransmission. Retransmitted packets create network congestion and heavy traffic. Errors, which are mainly caused by coupling effects, introduce crosstalk. This establishes a need for a coding technique for multiple bit error correction and avoiding crosstalk to form a reliable on-chip communication. In this paper, we propose Joint Crosstalk Avoidance with Multiple bit Error Correction (JCAMEC) coding technique which uses extended Hamming code and simple parity check code along with duplication. Duplicating the encoded bits provides the benefit of avoiding crosstalk. The coding technique in this work is placed in Network Interface (NI) to reduce the hardware overhead involved at every router in case of Hop to Hop error correction. However, to avoid the error propagation an error detector is placed at the router across each port, which consumes less area and power overhead compared to generic coding techniques. Evaluation and analysis is carried out based on the NI critical path delay along with the total power and area. Also, probability of residual error, power consumption and voltage swing of the link are estimated. The results demonstrate that JCAMEC coding technique outperforms the coding techniques considered for comparison and builds NoC with better reliability.