A FPGA Implementation of Hard Systematic Error Correcting codes based Matching of Data Encoded Architecture with Low-Complexity, Low-Latency
Suhas B. Shirol, S. Ramakrishna, Priyatamkumar, Rajashekar B. Shetta · 2018 Second International Conference on Electronics, Communication and Aerospace Technology (ICECA) · 2018
Nowadays to get error free data is toughest task. To verify whether the data is error free or not and decrease overall area and latency the new architecture has been designed which matches the data saved in the system and incoming data using Error Correcting Code (ECC).ECC basically consist of two parts parity part and raw data which are generated by encoder. In this method the matching of the data is made parallel so that we can further decrease the area and one more method has been designed called Buttery weight accumulator which correctly calculates the hamming distance. To still reduce the area a new technique has introduced in which we have used the modified XOR gate. This has been implemented using Xilinx Simulator and Spartan 6 FPGA board.