Low-Latency FIR Filter Structures Targeting FPGA Platforms
Piero Rivera Benois, Patrick Nowak, Udo Zölzer, Marcel Eckert, Bernd Klauer · 2018
research-article Share on Low-Latency FIR Filter Structures Targeting FPGA Platforms Authors: Piero Rivera Benois Dept. of Signal Processing and Communications, Helmut-Schmidt University Hamburg Dept. of Signal Processing and Communications, Helmut-Schmidt University HamburgView Profile , Patrick Nowak Dept. of Signal Processing and Communications, Helmut-Schmidt University Hamburg Dept. of Signal Processing and Communications, Helmut-Schmidt University HamburgView Profile , Udo Zölzer Dept. of Signal Processing and Communications, Helmut-Schmidt University Hamburg Dept. of Signal Processing and Communications, Helmut-Schmidt University HamburgView Profile , Marcel Eckert Dept. of Computer Engineering, Helmut-Schmidt University Hamburg Dept. of Computer Engineering, Helmut-Schmidt University HamburgView Profile , Bernd Klauer Dept. of Computer Engineering, Helmut-Schmidt University Hamburg Dept. of Computer Engineering, Helmut-Schmidt University HamburgView Profile Authors Info & Claims HEART 2018: Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable TechnologiesJune 2018 Article No.: 14Pages 1–7https://doi.org/10.1145/3241793.3241807Published:20 June 2018Publication History 1citation63DownloadsMetricsTotal Citations1Total Downloads63Last 12 Months10Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access