Enhanced AES Architecture using Extended Set ALU at 28nm FPGA
Nidhi Gaur, Anu Mehra, Pradeep Kumar · 2018
World has become digital nowadays and networking is a key feature of this changing globe. Key information of official transactions to social life of an individual, all lie on a network which has attracted researchers towards network security as an important issue to deal with. A number of encryption and decryption techniques have developed since years, Advanced Encryption Standard (AES) being the most popular and highly efficient. This paper proposes an extended implementation of 128 bit AES block along with four blocks of 32 bit Arithmetic and logic units (ALU). The extended set ALU with Manchester encoder decoder, Parity Generator, Parity checker, Binary to gray and Gray to Binary convertor is used for enhanced security. The proposed model provides flexibility at user level to switch between various security options. Complete design is implemented on 28nm zynq 7000 FPGA board using Xilinx Vivado tool.