A Simple Novel Floating Point Matrix Multiplier VLSI Architecture for Digital Image Compression Applications
Lakshmi kiran Mukkara, Kota Venkata Ramanaiah · 2018
For implementation of Low Power VLSI Architectures in the area of Digital Image Processing applications, Matrix Multiplication is a key arithmetic operation. To construct VLSI architectures with Low Power, High Speed and Low area, Matrix Multiplication design becomes complex. In this paper, a simple novel VLSI architecture for FPMM is presented. It is designed by considering Pseudo code for matrix multiplication, CSD multiplication algorithm for power reduction, Conventional floating point number format and Pipelining concept for improving speed. FPMM design is applicable for any arbitrary size of matrices by following matrix rules. This design can also give high precision output. Simulation results are perfectly matching with that of MATLAB results.