Design & Performance Analysis of Area Optimized in BPSK on NCO and High Speed 64 Bit-QAM with Gardner Algorithm
R. Ilaiyaraja, S. Sedhumadhavan · 2018
This project used its reconfigurable ability and high throughput performance, using Field Programmable Gate Array (FPGA). Our aim of this paper, BPSK system is designed in verilog for optimized area (as a single block to generate two signals). In order to reduced area have to using numerically controlled oscillator (NCO). By using this NCO system we can controlling the phase of the each carrier signal. The designs have been successfully verified by simulation and implementation. The drawback of BPSK system speed is very slow and this system is not suitable for high bit data rate. So that having to plan design and implementation of 64QAM (Quadrature Amplitude Modulation) for increasing the speed, flexibility, accuracy and configurability in designing and implementation. We can implemented gray code symbol mapping and differential code symbol mapping on 64QAM system.