Superscalar Encrypted RISC: The Measure of a Secret Computer
Péter Breuer, Jonathan P. Bowen, Esther Palomar, Zhiming Liu · 2018
Appropriately modifying the arithmetic in a processor causes data to remain in encrypted form throughout processing, providing a technical approach to privacy for the ordinary user against the operator and other powerful insiders. The theory has been verified in a prototype superscalar processor design that fully implements the OpenRISC processor standard, adapted for encrypted running. The processor runs in a (one-to-many) encryption in user mode, and runs unencrypted in operator mode. The AES-based models run at 104 Dhrystones MIPS on a 1GHz base clock, equivalent to a 433MHz classic Pentium. Experience lets us propose a modified RISC instruction set for encrypted working with which semantic security (relative to the security of the encryption) for user data against the operator is mathematically provable on this kind of platform, in conjunction with an 'obfuscating' compiler for user programs, though the operator has unrestricted runtime access to (encrypted) user data.