Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation
Louis Y.-Z. Lin, Charles H.‐P. Wen · IEEE Access · 2018
Shared-memory systems enable parallel computing for the automatic test pattern generation (ATPG). Although the existing techniques for parallel ATPG reach near-linear speedup, test inflation becomes a common problem in its practicality. Therefore, this paper proposes a multi-threaded test pattern generation calledMT-TPGthat can suppress test inflation and accelerate fault processing, simultaneously, to retain high parallelism. For suppressing test inflation,hard-fault shuffling(HFS) andconcurrent-fault interruption(CFI) are involved to avoid repeated detection of the same fault among different threads. For accelerating fault processing, thepotentially-droppable-fault removal(PDFR) andsingle-pattern parallel-fault simulation(SPPFSim) collectively drop not-yet-detected faults as early as possible for shortening the overall execution time of ATPG. According to our experimental results, theHFSandCFIcan successfully suppress test inflation toPDFRandSPPFSimcan achieve 13.7X speedup using 16 threads on average. As a result,MT-TPGis proven effective at unleashing parallelism with minimal test inflation on shared-memory systems.