Reloc — An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles
Bjorn Gottschall, Thomas B. Preuber, Akash S. Kumar · 2018
As programmable logic is conquering data centers, FPGA resources become a ubiquitously available commodity available through the cloud. In these ecosystems, their employment must advance to fit the role of a dynamically managed, shared resource within multi-user environments. Programmable hardware vendors provide engineering workflows that only start to acknowledge the requirements of this thriving application context, which makes resource regularization, design migratability and isolated execution imperatives. Quite a few academic efforts have aimed at the key technique of design relocation on top of the vendor-provided workflows. Regularly, critical shortcomings remain and, in all cases, the engineering procedure is ridiculously complex. This paper identifies the significant gaps left by previous approaches and describes a thoroughly automated workflow for building a system infrastructure on FPGA that makes it a resource that is manageable by the OS. It highlights an end-to-end workflow to enable (a) the out-of-context synthesis of end-user designs against a thin module interface defined by appropriate synthesis constraints, which are (b) universally employable to all the user slots provisioned on an appropriately partitioned device without re-synthesis and (c) will operate there appropriately isolated merely communicating to the user host application through privately allocated communication channels.