Data Plane Offloading on a High-Speed Parallel Processing Architecture
Danilo Cerović, Valentin Del Piccolo, Ahmed Amamou, Kamel Haddadou, Guy Pujolle · 2018
The throughput supported by network interfaces can be hardly followed by the packet processing speed in software. The processing rate is bounded due to the overheads imposed by the architecture of the network stack. For this reason, multiple research proposals try to offload packet processing on different types of hardware like GPUs and FPGAs. In this paper we present an architecture which offloads the data plane packet processing on a programmable hardware with parallel processing capability. For this purpose, we use the MPPA (Massively Parallel Processor Array) smart NIC from Kalray which offers the ODP API that can be used for packet processing. Our goal is to build a full mesh non-blocking layer 2 network. We implemented a TRILL protocol on the MPPA processor, which can be used as a basis for fabric network, but some other protocol may be used as well. Our performance evaluation shows that we can process TRILL frames at full-duplex line-rate (up to 40Gbps) for different packet sizes while reducing latency.