Frequent items counter based on binary decoders
Katsumi Inoue, Trong-Thuc Hoang, Cong‐Kha Pham · IEICE Electronics Express · 2018
In this paper, the hardware design of frequent items counter is proposed.The key idea is to create a matrix of binary-value by using an array of binary-decoder to decode all of the input items in parallel.After that, an array of population-count modules are applied to the rows of the matrix to generate counting results.The architecture was implemented with five options of bit/item from 6-bit/item to 10-bit/item, and seven options of count-register bit-width from 8-bit counters to 32-bit counters.Therefore, there were 35 different versions of implementation presented in this paper.Those implementations were built on the Field-Programmable Gate Array (FPGA) board of Altera Arria V SoC development kit.Also, they were synthesized to chips with the process technology of 65 nm Silicon On Thin Buried-Oxide (SOTB).The experimental results of the proposed architecture achieved outstanding timing performances compared to other attempts to date.