Low‐complexity and differential power analysis (DPA)‐resistant two‐folded power‐aware Rivest–Shamir–Adleman (RSA) security schema implementation for IoT‐connected devices
Saman Kaedi, Mohammad Ali Doostari, M. B. Ghaznavi‐Ghoushchi · IET Computers & Digital Techniques · 2018
The hardware security issues are emerging in crypto‐algorithms of embedded portable Internet‐of‐Things‐Devices (IoTD). The communication protocols/standards including MQTT (Message Queuing Telemetry Transport) are enforcing additional cares in device‐to‐system design perspectives. Due to computation‐capacity limitations (CCLs) in battery‐operated IoTD, heavy‐duty crypto‐algorithms are prohibited. This results in compromised hardware using lightweight algorithms. In this study, a new implementation schema for hierarchically‐connected IoTD for indoor applications is proposed. This schema allows the IoT network to utilise strong‐crypto‐algorithms (i.e. RSA) instead of lightweight algorithms (i.e. attribute‐based encryption (ABE)). Therefore, without increasing the consumption power or complexity, the security in the IoT network increases. This method brings about a new low CCL RSA with two‐folded power‐aware implementation. Furthermore, without complexity overhead, the proposed method is more secure than the conventional implementation due to the inherent countermeasure against the side‐channel attacks. The presented schema is implemented on a target IoT network, utilising in XC7A100T‐FPGA as IoT nodes. Furthermore, both the conventional and the proposed RSA‐2048 have been implemented in Spartan6‐LX75 on a SAKURA‐GW board. The results show that the proposed method has reduced the RSA execution time and consumption power of IoTD at about 50 and 60%, respectively. The most noticeable drawback of the current implementation is an overhead in the range of 30–53% on block‐random access memory (RAM) usage.