A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS
Minyi Lu, Ao Fan, Jiaming Xu, Weiwei Shan · 2018
Lightweight AES encryption circuits are significant to IoT applications to protect data, where very strict area and power constraints are required. In this paper, we propose a novel 8-bit datapath AES architecture aiming for a small area and a high energy efficiency. Firstly, our proposed design reduces the number of temporary data storage (IntermediateReg) to 40-bit from the originally 128-bit, which saves 68.75% intermediate registers. Secondly, only one S-Box is implemented in the design that is reused throughout the whole AES operations to achieve a low area. Thirdly, the architecture is further optimized to reduce the number of clock cycles by reusing S-Box in the key expansion and the data encryption module, leading to only 213 total cycles of latency in a complete encryption process. Simulation results under TSMC 28nm technology show that our proposed AES circuit consumes an area of 0.0028mm2, with an energy efficiency of 667Gbps/W (equivalent to 1.50 pJ/bit) and throughput rate of 30.05Mbps at 0.5V. This design achieves a high energy efficiency per unit area of 0.278 Gbps/(W·um2). This small area, high energy efficiency and relatively high throughput AES circuit is suitable for IoT applications.