An FPGA Synthesis of Face Detection Algorithm using HAAR Classifier
Archit Gajjar, Xiaokun Yang, Lei Wu, Hakduran Koc, Ishaq Unwala, Yunxiang Zhang, Yi Feng · 2018
This paper presents a synthesis of well-known Viola-Jones face detection algorithm on Xilinx software and platform - Vivado and field programmable gate array (FPGA) as Nexys 4 Artix-7 device. Compared with the prior work on the Altera platform proposed in [1], our work reduces the slice count by 1018. And additionally, the power consumption of the implementation is 714 mW, including 15% as the static cost and 85% as the dynamic power dissipation.