Delay based approach to Asynchronous Microprocessor Architecture
Avinash Paliwal · 2017
Today the microprocessor industry has come a long way from Intel 4-bit microprocessor 4004 to multicore processors. The industry has kept growing consistently with advancements in Very Large Scale Integration (VLSI), multicore processor architecture and other breakthroughs. But soon a limit will be reached as to how far we can squeeze transistors onto a chip. The steady growth in computing power will decline necessitating new breakthroughs in technology. Asynchronous microprocessor architecture might be one such way. This study describes a delay based design approach for a 4-bit asynchronous microprocessor. Delay blocks with delays marginally more than the executing blocks are used in conjunction to generate a ready signal to the Control Unit (CU). This ready signal is used by the control unit to determine the completion of current execution and signal the next execution block. Individual blocks like Program Counter (PC), Arithmetic Logic unit (ALU), instruction decoder and registers were designed and implemented in Very high-speed integrated circuit Hardware Description Language (VHDL). Basic design blocks were also tested on Altera DE0 Field Programmable Gate Array (FPGA) board.