Security Improvement of FPGA Design Against Timing Side Channel Attack Using Dynamic Delay Management
Pourya Bayat-Makou, Ali Jahanian, Media Reshadi · 2018
Side-channel attacks (SCAs) are known as the prominent vulnerabilities of the secure systems. In this paper, the sensitivity of the FPGA designs against the timing attack are analyzed and then, a dynamic technique is proposed to mitigate the possibility of timing side-channel attacks. The proposed technique decreases the dependency of the circuit delay against internal data. In the presented method, chains of inverters are added on the critical path dynamically according to the delay of the active path at runtime. Various scenarios of the adding delay chains including random delay and controlled delay are utilized to reach an optimum design. Finally, a timing analysis attack is applied to the FPGA hardware to evaluate the security improvement. The experimental results show that the dependency of the output delays to the internal values is reduced considerably, which indicates the system security improvement against the timing analysis attacks.