An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses
Pooneh Safayenikoo, Arghavan Asad, Farah A. Mohammadi · 2018
With technology scaling and increasing parallelism levels of new embedded applications, number of cores in chip-multiprocessors (CMPs) has been shifted from 100 to 1000 cores. To efficiently store and manipulate of large amount of data in future applications and, also, decreasing the gap between cores and off-chip memory accesses, the size of cache systems in CMPs has been dramatically increased. Since on-chip storage systems, particularly last level caches, occupy as much as 50% of the chip area, they are dominant leakage power consumer in future multi/many-core systems. In this context, power consumption becomes a primary concern in future CMPs because many of them are generally limited by battery lifetime. For future CMPs architecting, 3D stacking of last level caches (LLCs) has been recently introduced as a new methodology to combat to performance challenges of 2D integration and memory wall. However, the 3D design of LLCs incurs more leakage energy consumption compared to conventional cache architectures in 2Ds due to dense integration. In this paper, we use the non-uniform distribution of the accesses in banks of LLCs to decrease leakage energy. We propose a runtime cache architecture. The proposed architecture that is based on nonuniform cache architectures (NUCA) disables cache banks that have low accesses and leads to high energy-efficiency. The experimental results show that the proposed method improves energy-delay product by about 41% on average under PARSEC benchmarks compared to a recent technique named EECache.