Design of Optimal Elliptic Curve Cryptography by using Partial Parallel Shifting Multiplier with Parallel Complementary
S. Hemalatha, V. Rajamani, Velusamy Parthasarathy · 2017
High-speed Elliptic Curve Cryptography (ECC) modules implementation with less time, area, devices used is the recent research studies in cryptographic technology. The inclusion of modulus function in ECC contains several computations that lead to more time consumption and less speed. More multipliers and dividers utilization in ECC-based encryption/decryption required huge logic gates and registers. Hence, area and power consumption are more in ECC hardware unit. To overcome these problems, an enhanced ECC proposed in this paper. The framework optimizes the size of the multiplier and divider leads to a reduction of logic gates utilization. In our proposed work, we present a novel design structure for multiplier and divider based on ECC model defined by . During the encryption, the self-multiplication of the input data for n number of times creates the public key. The remainder obtained from modulo division is regarded as the corresponding encrypted form of input data. To perform these multiplication and modulo division, we present a novel Partial Parallel Shifting Multiplier (PPSM) and Parallel Complementary Method (PCM) to reduce the number of logic gates and improve the operational speed. The comparative analysis between the proposed (PPSM-PCM) with the existing ECC architectures regarding the parameters such as number of logic gates, LUTs, FFs, frequency, power consumption, delay rate and latency assures the suitability of high-speed ECC in real-time applications.