A Fault- Tolerant Routing Method for 2D-Mesh Network-on-Chips Based on the Passage of Fault Blocks
Yota Kurokawa, Masaru Fukushi · 2018
Toward the realization of dependable high-end consumer electronics products, this paper proposes a fault-tolerant routing method for 2D mesh Network-on-Chips (NoCs). Unlike the conventional fault-tolerant routing methods which always detour faulty nodes, the proposed method is based on a new concept; packets can pass through faulty nodes. For the method, we enhance the common NoC architecture and add switches and links around the each node. Simulation result shows that the proposed method reduces average communication latency by about 75.9%, compared with the conventional method.