Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs
Alexander A. Barkalov, Larysa Titarenko, Sławomir Chmielewski · Journal of Circuits Systems and Computers · 2018
A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.